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Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance
PHD24N03LT
SYMBOL
d
QUICK REFERENCE DATA VDSS = 30 V ID = 24 A
g
RDS(ON) 56 m (VGS = 5 V) RDS(ON) 50 m (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHD24N03LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
PIN 1 2 3 tab gate drain 1 source DESCRIPTION
SOT428 (DPAK)
tab
2
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 30 30 13 24 20 96 60 175 UNIT V V V A A A W C
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum footprint 50 MAX. 2.5 UNIT K/W K/W
1 it is not possible to make connection to pin 2 of the SOT428 package. December 1999 1 Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 12 A VGS = 5 V; ID = 12 A Tj = 175C Tj = 175C MIN. 30 27 1.0 0.5 -
PHD24N03LT
TYP. MAX. UNIT 1.5 50 45 10 0.05 7 2.3 5 12 50 30 36 3.5 7.5 460 144 78 2.0 2.3 56 50 104 100 10 500 V V V V V m m m nA A A nC nC nC ns ns ns ns nH nH pF pF pF
Gate source leakage current VGS = 5 V; VDS = 0 V Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 24 A; VDD = 15 V; VGS = 5 V
VDD = 15 V; RD = 0.6 ; VGS = 5 V; RG = 10 Resistive load Measured from tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 24 A; VGS = 0 V IF = 12 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V TYP. MAX. UNIT 1.05 50 100 24 96 1.5 A A V ns nC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. 15 UNIT mJ Drain-source non-repetitive ID = 12 A; VDD 15 V; VGS = 5 V; unclamped inductive turn-off RGS = 50 ; Tmb = 25 C energy
December 1999
2
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
PHD24N03LT
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
10
Transient thermal impedance, Zth j-mb (K/W) PHP24N03T
D= 1 0.5 0.2 0.1 0.05 0.1 0.02
P D tp D= tp T t
0
T
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.01
1us
10us 100us 1ms 10ms pulse width, tp (s)
0.1s
1s
10s
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Normalised Current Derating
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
20
ID, Drain current (Amps) 5V 15 V
PHP24N03LT 3.5 V
15
10
3V
5 VGS = 2.5 V Tj = 25 C
0 20 40 60 80 100 Tmb / C 120 140 160 180
0
0
5
10 15 20 25 VDS, Drain-Source voltage (Volts)
30
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
RDS(on), Drain-Source on resistance (Ohms) PHP24N03LT 3V VGS = 2.5 V
100
ID, Drain current (Amps)
PHP24N03T
0.12 0.1 0.08
RD
O S(
N)
D =V
S/
ID
10 us
100 us 10 DC 1 ms 10 ms Tmb = 25 C 1
0 0.06 0.04 0.02 Tj = 25 C
3.5 V 5V 15 V
1
10 VDS, Drain-source voltage (Volts)
100
0
5
10 15 ID, Drain current (Amps)
20
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
December 1999
3
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
PHD24N03LT
20
Drain current, ID (A) VDS = 25 V
PHP24N03LT
2.5
VGS(TO) / V max.
2
15
typ. 1.5
10
min. 1
5 175 C
Tj = 25 C
0.5
0
0
1
2 3 Gate-source voltage, VGS (V)
4
5
0 -100
-50
0
50 Tj / C
100
150
200
Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj
PHP24N03LT
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Sub-Threshold Conduction
15
Transconductance, gfs (S) VDS = 25 V Tj = 25 C
1E-01
1E-02 2% typ 98%
10
175 C
1E-03
5
1E-04
1E-05
0
0
5
10 Drain current, ID (A)
15
20
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
a 2
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
Capacitances Ciss, Coss, Crss (pF) Ciss
30V TrenchMOS
1000
PHP24N03LT
1.5
1
100
Coss Crss
0.5
Tj = 25 C
0 -100
-50
0
50 Tj / C
100
150
200
10
1
10 100 Drain-source voltage, VDS (V)
1000
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 12 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1999
4
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
PHD24N03LT
15
VGS, Gate-Source voltage (Volts) VDD = 15 V ID = 24 A Tj = 25 C
PHP24N03LT
20
Source-Drain diode current, IF(A) VGS = 0 V
PHP24N03LT
15
10
10
5
5
175 C
Tj = 25 C
0
0
0
5
10 15 Qg, Gate charge (nC)
20
25
0
0.2
0.4 0.6 0.8 1 Source-Drain voltage, VSDS (V)
1.2
1.4
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS
Fig.14. Typical reverse diode current. IF = f(VSDS); parameter Tj
December 1999
5
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped)
PHD24N03LT
SOT428
seating plane y A E b2 A A1 mounting base A2 D1
E1 D HE L2
2
L L1
1
b1 e e1 b
3
wM A c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 2.38 2.22 A1(1) 0.65 0.45 A2 0.89 0.71 b 0.89 0.71 b1 max. 1.1 0.9 b2 5.36 5.26 c 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 HE max. 10.4 9.6 L 2.95 2.55 L1 min. 0.5 L2 0.7 0.5 w 0.2 y max. 0.2
2.285 4.57
Fig.15. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".
December 1999
6
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
PHD24N03LT
7.0
2.15 2.5
1.5
4.57
Fig.16. SOT428 : soldering pattern for surface mounting.
December 1999
7
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHD24N03LT
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
December 1999
8
Rev 1.100

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